Study on warpage and stress of TSV wafer with ultra-fine pitch vias for high density chip stacking

Abstract

In this study, we demonstrated a TSV wafer with hybrid via with fine pitch of 6 μm and 9 μm. An effective finite element analysis (FEA) modeling methodology was developed for warpage and stress analysis by considering both silicon and Cu via effect. Based on the effective model, parametric studies were conducted for wafer warpage, including wafer annealing temperature, reticle size, via depth and TSV design. FEA simulation results show that critical parameters are annealing temperature and TSV density. Several stress analysis models were also discussed and compared. TSV stress is independent of TSV location on wafer. Parametric study was also conducted for stress analysis using the simplified TSV array model. In addition, thinning process affecting on stress was also investigated.