Publication | Closed Access
8-Layers 3D vertical RRAM with excellent scalability towards storage class memory applications
91
Citations
5
References
2017
Year
Unknown Venue
Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits8-Layers 3D3D MemoryElectronic DevicesMemory Device3D Ic ArchitectureElectrical EngineeringUltimate ScalabilityComputer EngineeringMicroelectronicsMemory ArchitectureThree-dimensional Heterogeneous IntegrationApplied PhysicsVertical RramSemiconductor MemoryBit Cost3D Integration
For the first time, we experimentally demonstrated a bit cost scalable (BiCS) 8-layer 3D vertical RRAM with ultimate scalability. The design of self-selective cell (SSC) with non-filamentary switching were successfully extended to 8 stacks and exhibits salient features, including high nonlinearity (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), forming free and high endurance (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ). An extremely scaled 3D structure with 5 nm size and 4 nm vertical pitch was further demonstrated. The sub μA operation current is quite promising for low power applications, but not good for sensing speed. A fixed bitline voltage sensing circuit was proposed to address the latency issue. Sub-μs read latency in bit sensing mode was successfully achieved.
| Year | Citations | |
|---|---|---|
Page 1
Page 1