A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration

Abstract

This paper presents a 2× time-interleaved 7-b 2.4-GS/s 1-then-2 b/cycle SAR ADC in 28-nm CMOS. The process-voltage-temperature sensitivity of a multi-bit SAR architecture has been improved by the proposed 1-then-2 b/cycle scheme with background offset calibration. With the pre-charge reduction scheme, the traditional large switching energy and time consuming pre-charge operation have been removed, which simultaneously enables a simple control logic without the need of a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</sub> voltage. Besides, a background offset calibration is implemented on chip which does not involve any extra phase or calibration input signal. Its operation is well embedded within the 1-then-2 b/cycle architecture, thus leading to a very minimal modification of the ADC core. With an improved fringing DAC structure and a high-speed dynamic logic circuit, a single-channel ADC can work at 1.2 GS/s under a 0.9-V supply. Using two-way time interleaving, the prototype samples at 2.4 GHz and consumes 5-mW power including the on-chip background offset calibration. It exhibits a 40.05-dB SNDR at Nyquist, leading to a Walden FoM of 25.3 fJ/conversion step. Measurement results show that the SNDR of the ADC can be kept above 38 dB at 2 GS/s under a wide range of temperature, supply, and input common-mode variation.