IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2018 · 101 citations · 15 references
EngineeringAerospace EngineeringElectrical EngineeringFault ToleranceMicroelectronicsSemiconductor DevicesDevice ReliabilityHardware Fault ToleranceMemory DevicesRadiation HardeningSemiconductor ReliabilityMemory Circuit DesignRadiation-hard DevicesRadiation-hard ElectronicsRadiation-hardened Integrated CircuitsRadiation-hardened MemoryRadiation-hardened Memory DevicesRadiation-hardening TechniquesRadiation-tolerant Electronics
In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both 0 → 1 and 1 → 0 single node upsets, with the increased read/write access time.
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