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Monolithically integrated Si gate-controlled light-emitting device: science and properties
126
Citations
39
References
2017
Year
EngineeringDevice IntegrationElectric Field ConfinementGate VoltageSemiconductor MaterialsIntegrated CircuitsSilicon On InsulatorSemiconductor DeviceSemiconductor DevicesElectronic DevicesElectronic EngineeringPhotonic Integrated CircuitPower SemiconductorsSemiconductor TechnologyPhotonicsElectrical EngineeringNew Lighting TechnologySemiconductor Device FabricationApplied PhysicsSi LightOptoelectronics
The study aims to create a p–n junction light‑emitting device that uses voltage driving via an insulated gate instead of conventional reverse‑current driving. The device is a three‑terminal Si emitter that employs injection‑enhanced Si in avalanche mode, confining the electric field to the corner of a reverse‑biased p⁺n junction. Light intensity varies linearly or quadratically with gate voltage or reverse bias, indicating that the device could enable large‑scale integration‑compatible emitters for inter‑ or intra‑chip signaling and contactless wafer testing.
The motivation of this study is to develop a p–n junction based light emitting device, in which the light emission is conventionally realized using reverse current driving, by voltage driving. By introducing an additional terminal of insulated gate for voltage driving, a novel three-terminal Si light emitting device is described where both the light intensity and spatial light pattern of the device are controlled by the gate voltage. The proposed light emitting device employs injection-enhanced Si in avalanche mode where electric field confinement occurs in the corner of a reverse-biased p+n junction. It is found that, depending on the bias conditions, the light intensity is either a linear or a quadratic function of the applied gate voltage or the reverse-bias. Since the light emission is based on the avalanching mode, the Si light emitting device offers the potential for very large scale integration-compatible light emitters for inter- or intra-chip signal transmission and contactless functional testing of wafers.
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