Negative Capacitance Carbon Nanotube FETs

Abstract

As continued scaling of silicon FETs grows increasingly challenging, alternative paths for improving digital system energy efficiency are being pursued. These paths include replacing the transistor channel with emerging nanomaterials (such as carbon nanotubes), as well as utilizing negative capacitance effects in ferroelectric materials in the FET gate stack, e.g., to improve sub-threshold slope beyond the 60 mV/decade limit. However, which path provides the largest energy efficiency benefits—and whether these multiple paths can be combined to achieve additional energy efficiency benefits—is still unclear. Here, we experimentally demonstrate the first negative capacitance carbon nanotube FETs (CNFETs), combining the benefits of both carbon nanotube channels and negative capacitance effects. We demonstrate negative capacitance CNFETs, achieving sub-60 mV/decade sub-threshold slope with an average sub-threshold slope of 55 mV/decade at room temperature. The average ON-current ( ${I}_{ \mathrm{ON}}$ ) of these negative capacitance CNFETs improves by $2.1\times $ versus baseline CNFETs, (i.e., without negative capacitance) for the same OFF-current ( ${I}_{ \mathrm{OFF}}$ ). This work demonstrates a promising path forward for future generations of energy-efficient electronic systems.