An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC

Abstract

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.