REMAP

Abstract

Even given PCM's attractive features that include high scalability and lower power, write endurance remains a critical issue that impedes the move for this technology to replace DRAM in main memory systems. The wear-out problem is further exacerbated by advances in future technologies, where cell sizes are reduced and process variation increases. When using PCMs, worn-out cells are permanently stuck at either '0' or '1'. Successful adoption of PCM requires recovery from multiple stuck-at faults in a data block. Current error correction schemes for PCMs have limited capabilities to tolerate faults.