An FPGA-based all-digital transmitter with 9.6-GHz 2nd order time-interleaved delta-sigma modulation for 500-MHz bandwidth

Abstract

An FPGA-based all-digital transmitter with 9.6-GHz 2nd order Time-Interleaved ΔΣ-modulation (TI-DSM) is presented. To improve the operation frequency of TI-DSM, bit separation architecture is proposed. This proposed architecture realizes the 1-bit digital transmitter with 500-MHz bandwidth. This is the widest bandwidth modulation among state-of-the-art FPGA-based all-digital transmitters.