Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications

Abstract

This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain voltage > 175 V, i.e. much lower than the target. An optimized LDMOS structure with a heavily doped extended P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> buried region is proposed and shown to be SEB resistant at the target drain voltage of 600 V, even for a highly-energetic ion with a linear energy transfer (LET) of 90 MeV/mg/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . TID simulations indicate that the main concern is the charge build-up in the thick field oxide (FOX). FOX positive charge density beyond 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> causes the breakdown voltage to drop below 200 V. Different oxide types which feature low “net” positive charge build-up have to be considered to allow for higher TID hardness. The proposed Si/SiC structure with a p+ region was shown to be resistant to a combined SEE and TID (in case of limited positive charge build-up in FOX) as well as combined SEE and high-temperature (up to 573 K) environments. In comparison to the equivalent Silicon-on-Insulator (SOI) LDMOS, the Si/SiC LDMOS structure with p+ buried region features similar immunity to SEB but allows for higher TID hardness.