Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links

Abstract

Traditional network-on-chip (NoC) interconnects follow conventional packet switching architectures that require multiple cycles to traverse each router hop. In addition, commonly used NoCs lack low-latency multicast replication and acknowledgment aggregation mechanisms that are required to efficiently handle the collective communication requirements exhibited by many modern applications. To address these issues, the single-cycle multihop asynchronous repeated traversal (SMART) NoC architecture is proposed. By using an efficient router-bypass mechanism, the SMART NoC enables single-cycle data transfers even between physically distant on-chip routers. However, enabling single-cycle hops over long metal wires restrict the achievable clock frequency of the system. In other words, increasing the NoC clock frequency lowers the number of hops that can be bypassed in a single cycle in a fully wireline SMART NoC. In this paper, we demonstrate that by integrating on-chip wireless links, a novel look-ahead bypass-request mechanism and a congestion-free broadcast routing methodology, it is possible to enable low-latency and energy efficient data transfers in the SMART NoC even when the system is designed with high clock frequencies. For the various applications considered in this paper, the wireless-enabled SMART NoC achieves on an average 41% reduction in message latency compared to the wireline SMART NoC. This network level improvement translates into 20% savings in full system energy-delay product.