A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip

Abstract

The power gating technique is an effective way to reduce the high static power consumption in a Network-on-Chip (NoC). However, with notable wakeup delay, the power gating technique incurs significant packet latency increase. In this paper, we propose a novel Duty Buffer (DB) structure and an efficient DB-based power gating scheme to overcome this drawback. By keeping minimal number of DB active to replace any sleeping virtual channel in a router, our approach can efficiently reduce the packet latency increase along the whole routing path. Compared with a conventional five-stage pipeline router without power gating, our approach, with only one flit depth of the DB, increases the average packet latency by only 9.67%, which is much less than 57% and 21.75% latency increase in related approaches. With small hardware overhead, our approach can save on average 52.19% of the total power consumption in a NoC, which is comparable with 59.39% and 57.05% power savings in related approaches.