A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture

Abstract

This paper presents a low-power 39.25-MHz crystal oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a crystal oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stackedamplifier crystal oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a crystal oscillator of -248 dBc/Hz with a power consumption of 19 μW and PN of -139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of -30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is -0.98 ppm in the first year (=365 days).