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A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT
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2017
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Low-power ElectronicsNon-volatile MemoryElectrical EngineeringSmart IotVlsi Design65-Nm Silicon-on-thin-boxNm 1.0EngineeringV 1.84Computer EngineeringSemiconductor MemorySleep ModeForward BbMicroelectronicsBeyond CmosPower-aware Design
A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.