Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

TLDR

Three‑dimensional integration of electronic chips is widely promoted as a promising solution to meet growing demands for performance, functionality, and power efficiency, yet numerous challenges have prevented its mainstream adoption at large scale. This paper surveys all popular 3D integration options and argues that an interposer‑based system‑level backbone is the most practical approach for large‑scale industrial applications and design reuse. We review key design‑automation challenges and promising solutions for interposer‑based 3D chips, outlining the need for a unified workflow, current solutions and future prospects for both digital and heterogeneous interposer stacks, state‑of‑the‑art testing challenges, and hardware security issues for large‑scale trustworthy integration.

Abstract

Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from “classical 2D chips” to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.