Area and power analysis of adiabatic 2×1 multiplexer design on 65nm CMOS technology

Abstract

Ultra-low-power CMOS IC has been required for the modern communication devices and biomedical systems. Performance of these systems can be evaluated in terms of less power dissipation during their operations. Efficient performance of digital systems has been required with less power dissipation. In CMOS circuits large amount of energy get dissipated in the form of heat during discharging phase. Adiabatic techniques can be used to prevent such losses by supplying the power back to the supply voltage. This paper presents 2x1 MUX adiabatic schematics which are designed and simulated using Microwind and DSCH deigning tools. MUX designs by using PFAL,ECRL, DPCAL and CAL adiabatic logics has been introduced. It is observed that MUX design by using ECRL has shown area efficiency and CAL design has shown the power efficiency as compared to other adiabatic designs. Area consumed by the ECRL design is 159.2 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and power dissipation of CAL MUX on 0.7V is 10.88 μW. ECRL has proved 15.5%, 9.85% and 10.76% area efficient as compared to CAL, DPCAL and PFAL adiabatic MUX design respectively.Parametric analysis has been done for all designs on 0.3V, 0.5V, 0.7V, 0.9V and 1.1V input supply voltage on 65nm technology. CAL adiabatic design has shown 4.04%, 12.84% and 14.46% power efficiency as compared to PFAL, ECRL and DPCAL MUX designs respectively at 0.7V input supply.