A full-duplex receiver with 80MHz bandwidth self-interference cancellation circuit using baseband Hilbert transform equalization

Abstract

To enable simultaneous full-duplex radios, self-interference (SI) cancellation (SIC) circuits that attain large cancellation bandwidths (BWs) are needed to support modern standards such as Long-Term Evolution (LTE). For mobile applications, SIC should be linear, tunable, fully monolithic (compact form factor) and must be implemented at the radio-frequency (RF) front-end. Emulating the group delay (GD) and complex impedance of the SI channel, an SIC circuit is proposed that achieves an 80 MHz of SIC BW using just a single tap delay. GD is estimated using frequency translations and baseband (BB) low pass filtering, and complex impedance is emulated using a vector modulator (VM). We prove that the combination of GD and VM results in a time-domain Hilbert transform equalization (HTE), enabling broadband cancellation and reducing the number of GD taps needed, thereby saving area. Implementing HTE at BB using passive circuits further reduces area, power consumption and maintains linearity. A prototype in 0.13-µm CMOS process occupies 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and attains 23 dB of SIC measured over an 80-MHz signal BW, while consuming 13 mW. Total power and area including the receiver is 64.4 mW and 0.72mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.