Bi-directional flip-chip 28 GHz phased-array core-chip in 45nm CMOS SOI for high-efficiency high-linearity 5G systems

Abstract

This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error <;0.8 dB and 5°, respectively at 25-33 GHz. In the RX mode, the measured gain is -10 dB and the NF is 10 dB with an input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 5 dBm. In the TX mode, the measured output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is -2 dBm. This work presents an efficient solution for the construction of high-linearity and high-power phased-array base-stations by combining GaAs front-ends with a passive silicon core chip.