Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip

Abstract

Fat-tree-based optical network-on-chip (FONoC) is an emerging architecture that enables next-generation computing platforms to achieve ultimate performance and energy efficiency. However, the architecture suffers from high insertion loss, which degrades energy efficiency and signal reliability severely. Focusing primarily on microring resonator (MR) drops, we analyze the relationship between the insertion loss caused by MR drops and the routing paths in the FONoCs. Our approach involves developing a simplified graph model named a drop-characterized fat-tree graph with vertex indexing. We propose three types of routing algorithms: 1) insertion loss-minimized deterministic routing; 2) minimized loss path-prioritized adaptive routing; and 3) insertion loss-constrained adaptive routing. Furthermore, we present the associated optical router architectures and additional insertion loss optimization by minimizing the number of waveguide crossings. Based on our simulation results for the latency, throughput, energy efficiency, and MR activation power, we discuss the tradeoffs and suggest appropriate optimization techniques to be adopted according to the priorities of the design goals.