Analysis of transient voltage fluctuations in FPGAs

Abstract

Due to recent technology scaling trends and increased circuit complexity, process and runtime variabilities are becoming major threats for correct circuit operation. Among these, transient voltage fluctuations appear to be the most critical issue, accounting for the biggest component of timing margin, at increased cost. As various design and workload parameters have an impact on voltage fluctuations, they need to be fully understood in order to design efficient countermeasures and margining. FPGAs are predestined for this analysis by allowing more control over such experiments at lower cost than ASICs. Even more, they highly suffer from the same issues, which are typically only handled by excessive and over-pessimistic timing margining built into the mapping tools. In this work, we implemented and calibrated sensors in configurable logic appropriate to observe delay changes caused by transient voltage fluctuations. We place them at multiple locations on the chip to evaluate temporal and spatial changes in timing margin due to different workload-characteristics. This analysis provides useful insights to designers for application mapping and workload scheduling.