Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

Abstract

In this paper, we study for the first time the impact of the design of gate sidewall spacer on the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) NWFETs with a gate- source/drain extension underlap. We demonstrate that the inclusion of a high-κ spacer over the source/drain extension region in the conventional NWFETs results in a suppressed lateral band-to-band tunneling (L-BTBT) GIDL. Furthermore, we also show that a gate-source/drain extension underlap architecture in NWFETs not only reduces the transverse BTBT GIDL but also mitigates the L-BTBT. However, the inclusion of a high-κ spacer in the underlapped NWFET leads to an enhanced L-BTBT and an increased off-state current compared with the underlapped NWFET with air spacer unlike FinFETs. In addition, we also study the impact of nanowire diameter and underlap length on L-BTBT GIDL of NWFETs. Furthermore, we demonstrate that the inclusion of the high-κ spacer increases the intrinsic delay owing to an increased fringe capacitance. Therefore, we provide the necessary design guidelines for performance optimization of NWFETs in the sub-10-nm regime.