A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

Abstract

Thanks to the high flexibility in matching the channel frequency response and the compatibility with simple adaptation techniques, Finite Impulse Response (FIR) filters enhance the equalization performances of high-speed wireline receivers. This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed. A thorough system analysis, aimed at deriving the specifications for circuits design, suggests four taps, with a tap-to-tap delay in the range 0.5-1 UI, as optimal compromise among complexity (hence power dissipation) and equalization performances. To keep high SNR, a new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude. Measurements are shown at 25 Gb/s for both Non Return to Zero (NRZ) and Pulse Amplitude Modulation (PAM)-4 signals. With a core power dissipation of 25 mW from 1-V supply, the proposed FIR filter recovers 20- and 9-dB channel loss for NRZ and PAM-4, respectively, with horizontal eye openings of 50% and 30%. Compared with the previously reported FIR filters for wireline links at comparable speed, the proposed realization achieves excellent equalization performance with the best power efficiency of 1 mW/Gb/s.