Present and future thermal interface materials for electronic devices

TLDR

Packaging electronic devices faces growing challenges as performance and power rise, feature sizes shrink, and reliable operation demands efficient heat transfer from ICs to heat sinks, with projected 14 nm chips exceeding 100 W cm⁻² power density and <0.2 °C W⁻¹ thermal resistance, making the thermal interface material the main bottleneck. This review evaluates the current state of the art of thermal interface materials. The review discusses thermal surface interaction theory, measurement techniques, TIM reliability, and next‑generation TIMs for Internet of Things thermal solutions.

Abstract

Packaging electronic devices is a growing challenge as device performance and power levels escalate. As device feature sizes decrease, ensuring reliable operation becomes a challenge. Ensuring effective heat transfer from an integrated circuit and its heat spreader to a heat sink is a vital step in meeting this challenge. The projected power density and junction-to-ambient thermal resistance for high-performance chips at the 14 nm generation are >100 Wcm−2 and <0.2 °CW−1, respectively. The main bottleneck in reducing the net thermal resistance are the thermal resistances of the thermal interface material (TIM). This review evaluates the current state of the art of TIMs. Here, the theory of thermal surface interaction will be addressed and the practicalities of the measurement techniques and the reliability of TIMs will be discussed. Furthermore, the next generation of TIMs will be discussed in terms of potential thermal solutions in the realisation of Internet of Things.