Effect of interconnect parasitic variations on circuit performance parameters

Abstract

Interconnects are integral part in the chip design which plays a major role in circuit performance in DSM technology. Due to the presence of parasitic such as Resistance, Capacitance components, signal degradation and delayed problems may occur. Now days because of technological advances, number of nodes increasing in circuits, there by introducing more parasitic in multi nodes which will effect on the circuit performance in terms of delay and power. With this motivation, here we have presented simulation analysis of the effect of interconnects due to parasitic and load on the circuit performance parameters in various DSM technologies. All simulations have done by considering the simple RC interconnect with a driver and load concepts. For the simulated interconnect model with variable lengths, delay and PDP values are estimated. The performance metrics indicates, there is a liner increment with change in load, 5 to 10% variations in same technology for variable lengths of interconnect and 40 to 50% variation in different technologies.