7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fs<inf>rms</inf>-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate

Abstract

In recent years, the explosive growth of handheld smart devices has demanded increasing network capacity and higher data-rate. With around 1GHz bandwidth in the 5GHz UNII frequency band, 802.11ac offers great flexibility in utilizing a wider signal bandwidth and more complex modulation scheme to achieve the PHY rate up to 1.733Gb/s with VHT160 2×2 MIMO. The increased signal bandwidth from 80MHz (Stage1) to 160MHz (Stage2) poses stringent design challenges for radio transceivers, such as tighter frequency synthesizer phase-noise requirement for better EVM floor, techniques of using integrated high-power PAs for achieving 160MHz operation, and overcoming the effect of LPF 3dB-corner-mismatch-induced Frequency-Dependent IQ imbalance (FD-IQ) [1] due to finite OP-Amp Gain-BW product and submicron process gradient effect. This paper describes a monolithic MIMO 802.11ac Stage-2 Wi-Fi SoC chip with integrated dual-band PA's, LNA's, and T/R switches.