Nanotube Junctionless FET: Proposal, Design, and Investigation

Abstract

In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.