Structural advantages of silicon-on-insulator FETs over FinFETs in steep subthreshold-swing operation in ferroelectric-gate FETs

Abstract

In this paper, we discuss the subthreshold operation of fully depleted silicon-on-insulator FETs (SOI-FETs) and FinFETs, with embedded ferroelectric negative-capacitance gate insulators, using technology computer-aided design simulations. SOI-FETs with ultrathin buried-oxide layers and appropriate workfunctions for bottom electrodes are found to be more preferable to attain steep subthreshold swings lesser than 60 mV/decade, because SOI-FETs can effectively enable a voltage drop in the ferroelectric layer, even though the degree of matching of the depletion capacitance and the ferroelectric gate insulator capacitance is almost the same in SOI-FETs and FinFETs. These results give a novel insight into how the subthreshold swing can be improved in ferroelectric-gate MOSFETs.