Review on realization of AES encryption and decryption with power and area optimization

Abstract

In this project, a hardware implementation of the AES-256 encryption and decryption algorithm is proposed. The AES cryptography algorithm can be used to encryption and decryption blocks of 128 bits and is capable of using cipher keys of 256 bits. Feature of the proposed pipeline design is depending on the round keys, which are consumed different round of encryption, are generated in parallel way with the encryption process. This lowers delay of the each round of encryption and reduces the encryption delay of a plaintext block. Xilinx ISE.14.7 (64-bit) is used for simulation by using VHDL and hardware implementation on FPGA (Xilinx Spartan 6 or Altera Cyclone 2 FPGA device).