Measuring error-tolerance in SRAM architecture on hardware accelerated neural network

Abstract

Hardware accelerators for convolutional neural network (CNN) accompany a large amount of SRAM in order to reduce the number of expensive off-chip DRAM accesses. This design trend gives implications to architects: the SRAM area will dominate the entire chip area for the future CNN accelerators. Since the probability of soft errors such as energetic particle strikes goes as the density of SRAM, errors on memory sub-system will become a major concern as process technology scales. In this paper, we investigate the necessity of a fault-tolerant memory system, against such soft errors, in hardware accelerated neural network. We found that convolutional layers have different error tolerance from each other. The error tolerance of a layer tends to get worse as it goes on the output layer.