Coarse grained reconfigurable architectures in the past 25 years: Overview and classification

TLDR

Reconfigurable architectures are increasingly popular as general‑purpose compute performance growth slows, with FPGA designs evolving toward coarse‑grain architectures that incorporate DSP blocks and heterogeneous processors. The study seeks to offer an overview and classification of CGRA architectures, establish a clear definition of CGRAs, and pinpoint future research topics essential to unlocking their full potential. To achieve this, the authors compile and systematically classify existing CGRA designs, presenting a taxonomy that delineates architectural features and research directions.

Abstract

Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable Architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable logic. In the past 25 years, several CGRAs have been published. In this paper an overview and classification of these architectures is presented. This work also provides a clear definition of CGRAs and identifies topics for future research which are key to unlock the full potential of CGRAs.