Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

TLDR

The paper proposes a highly efficient loop‑based interconnect modeling methodology for multigigahertz clock network design and optimization. The authors develop closed‑form loop resistance and inductance models for fully shielded global clock interconnects that capture high‑frequency effects, and validate them against electromagnetic simulations and measurements from a Power4 chip. The methodology significantly improves simulation efficiency, enabling rapid physical design exploration, and the authors demonstrate interconnect performance optimizations with accompanying design guidelines.

Abstract

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.