FINN

TLDR

Convolutional neural networks are highly redundant, allowing high accuracy even when weights and activations are binarized. This work introduces FINN, a framework for rapidly building flexible FPGA accelerators using a heterogeneous streaming architecture. FINN maps binarized neural networks to hardware via novel optimizations, implementing fully connected, convolutional, and pooling layers with per‑layer compute resources tuned to user‑specified throughput. On a ZC706 FPGA consuming <25 W, FINN achieves 12.3 M images/s (0.31 µs latency, 95.8 % accuracy on MNIST) and 21.9 k images/s (283 µs latency, 80.1 % on CIFAR‑10, 94.9 % on SVHN), the fastest rates reported for these benchmarks.

Abstract

Research has shown that convolutional neural networks contain significant redundancy, and high classification accuracy can be obtained even when weights and activations are reduced from floating point to binary values. In this paper, we present FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture. By utilizing a novel set of optimizations that enable efficient mapping of binarized neural networks to hardware, we implement fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements. On a ZC706 embedded FPGA platform drawing less than 25 W total system power, we demonstrate up to 12.3 million image classifications per second with 0.31 μs latency on the MNIST dataset with 95.8% accuracy, and 21906 image classifications per second with 283 μs latency on the CIFAR-10 and SVHN datasets with respectively 80.1% and 94.9% accuracy. To the best of our knowledge, ours are the fastest classification rates reported to date on these benchmarks.