A Quad-Band CMOS Linear Power Amplifier for EDGE Applications Using an Anti-Phase Method to Enhance its Linearity

Abstract

This work describes the use of an anti-phase method to enhance the linearity of a quad-band CMOS linear power amplifier for EDGE applications. The anti-phase method is applied in a CMOS process, by studying the gm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> characteristic of the transistor and then operating the drive stage in the subthreshold region to cancel the nonlinearity of the power stage. The power amplifier is fabricated with a 0.11 μm RF CMOS process and packed with a 44-pin QFN package. It operates in the GSM-800, EGSM-850, DCS-1800, and PCS-1900 bands. Application of an EDGE signal of 2.96 dB PAPR gives measured results of 26.2 and 26.7 dBm of average output power and 19.4% and 25.6% of PAE at 915 and 1910 MHz, respectively. No digital pre-distortion and off-chip components are present.