An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture

Abstract

A high-speed low-complexity time-multiplexing Reed-Solomon (RS)-based forward error correction (FEC) architecture based on pipelined truncated inversionless Berlekamp-Massey (pTiBM) algorithm is presented. The proposed architecture has very high speed and very low hardware complexity compared with conventional RS-based FEC architectures. A high-throughput data rate is facilitated by employing a three-parallel processing pipelining technique and modified syndrome computation block. The time-multiplexing method for pTiBM architecture is used in the parallel RS decoder to reduce hardware complexity. The proposed architecture has been designed and implemented with 90-nm CMOS technology. Synthesis results show that the proposed 16-channel Reed-Solomon-based FEC architecture requires 417,600 gates and can operate at 640 MHz to achieve a throughput of 240 Gb/s.