Future BiCMOS technology for scaled supply voltage

Abstract

A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>