2003 · 58 citations · 2 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignBipolar Junction TransistorsComplementary Metal-oxide-semiconductor TechnologyField-effect TransistorsIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsVoltage ScalingBicmos TechnologyCircuit ConfigurationCmos ScalingHigh-voltage Power SupplyLow-voltage Cmos DesignSupply Voltage OptimizationVoltage
A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array
M. Odaka, Kaori Nakamura, Kayoko Eno et al. · 2003 · 25 citations
Engineering, Computer Engineering, Electrical Engineering +16