A placement and routing algorithm for quantum-dot cellular automata

Abstract

The beyond silicon nanotechnologies create the possibility to develop new logic devices. In special, Quantum-dot Cellular Automata (QCA) technology opens new opportunities for saving power and achieving high performance clock rates. QCA technology circuit design imposes several challenges to be adressed by design tools. This paper proposes a new placement and routing algorithm to automatically design QCA logic circuits. The proposed solution ensures the correct operation by using an universal clock scheme that creates a layer to decouple the low level synchronization task from logic level. The technology layer is regular and scalable. The automatic generated layouts are competitive in terms of area when compared to handmade layouts. In comparison to previous automatic generators, the proposed approach saves area and provides more flexibility.