Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

Abstract

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices