A high speed superscalar PA-RISC processor

Abstract

A novel processor implementing Hewlett-Packard's PA-RISC 1.1 (precision architecture-reduced instruction set computer) has been designed. A single chip implemented in a 0.8- mu m three-level metal CMOS technology includes the integer processor and a floating point coprocessor. The design operates at 100 MHz and is the first superscalar PA-RISC design. The processor cache is a large configurable memory implemented with industry standard SRAMs (static RAMs). High performance is achieved by high-frequency operation and a variety of techniques used to reduce the average number of cycles per instruction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>