2011 · 32 citations · 16 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignParallel ComputingDigital Signal ProcessingMemory Hierarchy OptimizationParallel ArchitecturesPipeline ParallelismPower OptimizationWireless NetworksArea EfficiencyArea-efficient DesignDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksEnergy-efficient Signal ProcessingPower ConsumptionPower Consumption OptimizationWireless Personal Area Networks
This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
16
An algorithm for the machine calculation of complex Fourier series
J.W. Cooley, John W. Tukey · Mathematics of Computation · 1965 · 12.2K citations