ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications

Abstract

Network-on-Chip (NoC) has emerged as a promising paradigm to largely alleviate the limitations exhibited by the shared-bus based systems in current System-On-Chip (SoC). These problems include the lack of scalability, clock skew, lack of support for concurrent communication, and increasing power consumption. Based upon a packet/flit switching scheme, NoC allows a concurrent transmission of data providing a higher bandwidth and performance. In this paper, we present an optimized version of our earlier design OASIS-2, called ONoC-SPL, that employs a Short-PassLink (SPL) customization which aims to reduce the communication latency for performance enhancement in data-intensive computation applications. In order to evaluate its performance and hardware complexity accurately, we prototyped ONoCSPL on FPGA using two traffic patterns (Dimension-reversal and Hotspot) and also a real application (JPEG encoder). Evaluation results showed that ONoC-SPL reduces the execution time by 30.1% and enhances the throughput by 32.3% when compared with the earlier design. This performance improvement came with only an area utilization cost under the 5% and a slight 0.49% power overhead.