A 2GHz 16dBm IIP3 low noise amplifier in 0.25μm CMOS technology

Abstract

A 2GHz LNA implemented in a 0.25/spl mu/m CMOS technology delivers 14dB gain, 2.8dB NF and 16dBm IIP3. High linearity is obtained by a third-harmonic cancellation technique using a stacked triode structure with differential signals. The method, based on DC non-linear characteristics, improves delay equalization from DC-2GHz with a 17% power increase, 0.8dB gain reduction, and <0.1dB NF increase.