2003 · 23 citations · 0 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignElectronics TechnologyIntegrated Circuit DesignIntegrated Circuit DevicesSemiconductor Device MaterialsHigh-speed Cmos DesignLogic Gate DelaySilicon Carbide (Sic) Materials
A 0.5- mu m SICOS (sidewall base contact structure) technology is discussed. U-groove isolation technology and 0.5- mu m fabrication technology reduce the transistor size to 60 mu m/sup 2/. The use of a reduced-resistance base polysilicon electrode and a shallow epitaxial layer improves the emitter-coupled logic (ECL) gate delay time by 20% and 30%, respectively. A typical gate delay time of 29 ps and a minimum gate delay time of 27 ps at a switching current of 1.2 mA and an emitter size of 0.4 mu m*2.4 mu m were realized. This U-groove isolated SICOS device is suitable for very-high-speed VLSIs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>