A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)

Abstract

A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications