4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking

Abstract

To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFYM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 mum 1P5M CMOS process. The core size was 10.8 mum x 10 S mum. The power consumption of the ILO is 9.6 muW at 250 MHz, and 1.47 mW at 4.8 GHz. The phase noise is -108 dBc/Hz at 1 MHz offset. For a ten-times frequency multiplier, output phase noise is 10 JB larger than the input phase noise below 10 kHz offset, which is the theoretical limit.