Dielectric resurf: breakdown voltage control by STI layout in standard CMOS

Abstract

We demonstrate a novel device concept, in which junctions (active regions in CMOS) are interleaved with dielectric regions (STI) in order to increase the junction breakdown voltage. Experiments performed in a standard 90 nm CMOS process show an increase in breakdown voltages of extended drain MOSFETs from 15 to 45 V. This approach gives designers an extra degree of freedom to integrate high voltages in any standard CMOS process by STI layout design only, without the need for process modifications.