Memristor based STDP learning network for position detection

Abstract

Most neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights three basic learning rules - winner-take-all (WTA), spike timing dependent plasticity (STDP), and inhibition of return (IOR). It also gives a design example implementing WTA combined with STDP in a position detector. A CMOS and an MMOST (Memristor-MOS Technology) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout was done in 130 nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes 2.9×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area, 55 μW max power, and requires a 3 dB SNR. On the other hand, the MMOST design consumes 6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 15 μW max power, and requires a 4.8 dB SNR.