Device integration for ESD robustness of high voltage power MOSFETs

Abstract

The ESD robustness of a power MOSFET device is addressed in this paper. It is shown that by a novel device integration of the power output transistor with SCR, the ESD performance can be improved from less than 2 kV to greater than 6 kV. This is accomplished with no impact on the transistor performance or its application in circuit design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>