IEEE Transactions on Circuits and Systems I Regular Papers · 2016 · 19 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog Integrated CircuitsBuilt-in Self-testCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignAnalog Built-in Self-testBuilt-in Self-test For Analog CircuitsCmos Analog Integrated CircuitsDynamic RangeEmbedded TestMixed-signal Built-in Self-testMixed-signal TestQuantization Noise
This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio ΣΔ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.
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