On the parallelization approaches for Intel MIC architecture

Abstract

The Intel MIC architecture is one of the main processor architectures used for the production of computational accelerators. Increasing energy and cost-effciency of accelerators is one important option for building new HPC systems. However, the effective use of accelerators requires careful optimization on all stages of the algorithm and use of appropriate parallelization approaches. In the domain of statistical methods the quasi-Monte Carlo methods present distinct challenges when thousands of computational cores are to be involved in a computation. In this paper we describe in detail and study the performance of algorithms for generating some popular low-discrepancy sequences, aimed at devices with Intel MIC architecture. By leveraging the powerful vector instructions of the Intel MIC architecture to process many coordinates of the sequences in parallel, we obtain fast implementations that can be plugged-in in any parallel quasi-Monte Carlo computation. We present extensive numerical and timing results that demonstrate the benefit of our algorithms and their parallel effciency. The effects of using hyperthreading are also studied. The generation routines are provided under the GPL.