2016 · 19 citations · 1 references
EngineeringElectrical EngineeringDesign OptimizationLow-power DesignMicroelectronicsCmos Circuit DesignLow-noise Circuit DesignNoise In Analog CircuitsNoise ReductionPower OptimizationTransistor BiasingBiasing TechniquesLow-noise AmplifiersLow-power Amplifier DesignLow-power Cmos DesignPower ConsumptionPower Consumption ModelingPower Consumption OptimizationUltra-low-power Cmos
In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.
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